cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 1/9 mtn6515j3 cystek product specification n -channel logic level enha ncement mode power mosfet mtn6515j3 features ? low gate charge ? simple drive requirement ? pb-free lead plating equivalent circuit outline absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 150 gate-source voltage v gs 16 v continuous drain current @ t c =25 c i d 20 continuous drain current @ t c =100c i d 14 pulsed drain current *1 i dm 60 avalanche current i as 20 a avalanche energy @ l=0.1mh, i d =10a, r g =25 e as 5 repetitive avalanche energy @ l=0.05mh *2 e ar 2.5 mj total power dissipation @t c =25 60 total power dissipation @t c =100 pd 30 w operating junction and storage te mperature range tj, tstg -55~+175 c note : *1 . pulse width limited by maximum junction temperature *2. duty cycle 1% to-252ab to-252aa mtn6515j3 g gate d drain s source g d s g d s bv dss 150v i d 20a r ds(on) @v gs =10v, i d =15a 60m (typ) r ds(on) @v gs =5v, i d =10a 59m (typ) r ds(on) @v gs =3v, i d =3a 60m (typ)
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 2/9 mtn6515j3 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 2.5 c/w thermal resistance, junction-to-ambient, max r th,j-a 100 c/w characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static v gs(th) 0.45 0.8 1.20 v v ds =v gs , i d =250 a i gss - - 100 na v gs = 12, v ds =0 - - 1 v ds =120v, v gs =0 i dss - - 25 a v ds =100v, v gs =0, t j =125 c - 60 75 v gs =10v, i d =15a - 59 75 v gs =5v, i d =10a r ds(on) *1 - 60 75 m v gs =3v, i d =3a g fs *1 - 48 - s v ds =5v, i d =10a dynamic qg *1, 2 - 30 - qgs *1, 2 - 4.8 - qgd *1, 2 - 16 - nc i d =10a, v ds =80v, v gs =5v t d(on) *1, 2 - 23 - tr *1, 2 - 22 - t d(off) *1, 2 - 91 - t f *1, 2 - 63 - ns v ds =75v, i d =1a, v gs =4.5v, r g =6 ciss - 2282 - coss - 120 - crss - 66 - pf v gs =0v, v ds =25v, f=1mhz source-drain diode i s *1 - - 20 i sm *3 - - 60 a v sd *1 - 0.85 1.3 v i f =i s , v gs =0v trr - 50 - ns qrr - 120 - nc i f =20a, di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping marking mtn6515j3 to-252 (pb-free lead plating package) 2500 pcs / tape & reel n6515
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 3/9 mtn6515j3 cystek product specification typical characteristics typical output characteristics 0 10 20 30 40 50 60 024681 0 brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage 10v,9v,8v,7v,6v,5v,4v,3v v ds , drain-source voltage(v) i d , drain current (a) v gs =2v i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =1.5v v gs =2.5 v v gs =3v v gs =4.5 v v gs =10v v gs =1.8 v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0246810 i dr , reverse drain current(a) v sd , source-drain voltage(v) v gs =0v tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 40 80 120 160 200 02468 v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) 10 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =15a r ds( on) @tj=25c : 60 m i d =15a
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 4/9 mtn6515j3 cystek product specification typical characteristics (cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -60 -20 20 60 100 140 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =10 gate charge characteristics 0 2 4 6 8 10 0 1020304050 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =10a v ds =80v v ds =50v maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) t c =25c, tj=175c v gs =10v, jc =2.5c/w single pulse dc 100ms r dson limited 1s 100 s 1ms 10ms maximum drain current vs case temperature 0 5 10 15 20 25 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =2.5c/w
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 5/9 mtn6515j3 cystek product specification typical characteristics (cont.) typical transfer characteristics 0 10 20 30 40 50 60 70 024681012 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v power derating curve 0 10 20 30 40 50 60 70 80 0 25 50 75 100 125 150 175 200 t c , case temperature() p d , power dissipation(w) transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =2.5c/w
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 6/9 mtn6515j3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 7/9 mtn6515j3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 8/9 mtn6515j3 cystek product specification to-252ab dimension *: typical inches millimeters inches marking: style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-252ab plastic surface mount package cystek package code: j3 device name date code n6515 4 millimeters dim min. max. min. max. dim min. max. min. max. a 0.087 0.094 2.200 2.400 e *0.091 *2.300 a1 0.000 0.005 0.000 0.127 e1 0.177 0.185 4.500 4.700 b 0.053 0.065 1.350 1.650 h 0.118 ref 3.000 ref b 0.020 0.028 0.500 0.700 k 0.197 ref 5.000 ref b1 0.028 0.035 0.700 0.900 l 0.374 0.390 9.500 9.900 c 0.017 0.023 0.430 0.580 l1 0. 100 0.114 2.550 2.900 c1 0.017 0.023 0.430 0.580 l2 0.055 0.070 1.400 1.780 d 0.250 0.262 6.350 6.650 l3 0.024 0.035 0.600 0.900 d1 0.205 0.213 5.200 5.400 p 0.028 ref 0.700 ref e 0.213 0.224 5.400 5.700 v 0.209 ref 5.300 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead : pure tin plated ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0
cystech electronics corp. spec. no. : c739j3 issued date : 2009.10.19 revised date : 2012.11.27 page no. : 9/9 mtn6515j3 cystek product specification to-252aa dimension marking: style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-252aa plastic surface mount package cystek package code: j3 device name date code n6515 1 2 3 4 inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.087 0.094 2.200 2.400 e 0.086 0.094 2.186 2.386 a1 0.000 0.005 0.000 0.127 e1 0.172 0.188 4.372 4.772 b 0.039 0.048 0.990 1.210 h 0.163 ref 4.140 ref b 0.026 0.034 0.660 0.860 k 0.190 ref 4.830 ref b1 0.026 0.034 0.660 0.860 l 0.386 0.409 9.800 10.400 c 0.018 0.023 0.460 0.580 l1 0.114 ref 2.900 ref c1 0.018 0.023 0.460 0.580 l2 0.055 0.067 1.400 1.700 d 0.256 0.264 6.500 6.700 l3 0.024 0.039 0.600 1.000 d1 0.201 0.215 5.100 5.460 p 0.026 ref 0.650 ref e 0.236 0.244 6.000 6.200 v 0.211 ref 5.350 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead : pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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